Data Acquisition with Zynq + FreeRTOS+TCP/IP Stack

This video demonstration was originally intended to be a part of my "Learning VHDL" series. However, this project ended up having both hardware (i.e. HDL) and software components to it, so I decided to bundle all recent videos related to audio as its on series. One key point I neglected to mention in the video is the fact I'm intentionally trying to implement modules with variations of the AXI4, since I have to yet write anything blog-related on the topic but I constantly use it. Source code and more information on the project itself: (Programmable) Hardware: https://goo.gl/2DRi3j Software: https://goo.gl/jwbzHF Blog and project website: https://www.powellprojectshowcase.com