The World's Fastest ADC - EEs Talk Tech #13

Building ADCs and specs that might surprise you! Click to subscribe! ► http://bit.ly/Scopes_Sub ◄ electrical engineering podcast: https://eestalktech.com More links: How to pick an oscilloscope bandwidth - app note: http://literature.cdn.keysight.com/litweb/pdf/5989-5733EN.pdf Bandwidth and measurement accuracy - app note: http://literature.cdn.keysight.com/litweb/pdf/5991-0662EN.pdf Evaluating Oscilloscope Vertical Noise Characteristics - app note: http://literature.cdn.keysight.com/litweb/pdf/5989-3020EN.pdf Making an ASIC - blog: https://community.keysight.com/community/keysight-blogs/oscilloscopes/blog/2017/05/15/creating-an-asic-our-quest-to-make-the-best-cheap-oscilloscope How to get an Oscilloscope Bandwidth of over 16 GHz - App Note http://literature.cdn.keysight.com/litweb/pdf/5990-6515EN.pdf Intro: Mike is an ASIC planner on the ASIC Design Team What is an ADC? Analog vs. Digital ASICs? Three camps of ASICs: 1. Signal conditioning 3. Signal processing (digital) 2. In the middle is a convertor, either digital to analog (DAC) or analog to digital (ADC) 1:50 Signal conditioning ASICs can be very simple or very complicated e.g. Stripline filters are simple, oscilloscope front ends aren't 2:45 Converter vs. an analog chip with some digital functionality A converter has both digital and analog and a digital interface, like an I2C or SPI interface. It is digital in, analog out. 4:25 How do you get what's happening into the analog world into a digital interface, and how fast can you do it? 4:35 Mike did a basic ADC design in school Ladder converter, or "thermometer code" is the most basic of ADC architectures. 6:00 Slow ADC can use single ended CMOS, faster might use parallel LVDS, now it's almost always SERDES for highest performance chips 6:35 The world's fastest ADC? 6:55 Why do we design ADCs? We usually don't make what we can buy off the shelf. Nyquist rate determines sample rate, for example a 10 GHz signal needs to be sampled at 20 - 25 gigasamples 8:45 Then there's vertical resolution, number of bits. ADCs generally have two main specs, speed (sample rate) and vertical resolution. 9:00 The ability to measure time very accurately is often most important, but people often miss the noise side of things. 9:45 Normally, we oversimplify into just two specs. But, there's more than that. For example, bandwidth, frequency flatness, noise, and SFDR 10:20 It's much easier to add bits to an ADC design than it is to decrease the noise. 10:42 Noise floor and SFDR and SNR measure how good an analog to digital converter really is. SFDR means "spurious free dynamic range" and SNR is "signal to noise ratio" 11:00 Third tier things you need to worry about are error codes, especially for instrumentation. For some folding architectures and successive approximation architectures there can be big errors. This is ok for communication systems but not for oscilloscopes 12:30 So, you have to watch out for a lot of other things in ADC. 12:45 Where does ADC noise come from? It comes from both the ADC and from the system. 13:00 So, we start with a noise budget, and allocate the budget to different blocks of the oscilloscope or instrument. 13:35 Is an ADC the ultimate ASIC challenge? It's both difficult analog design and high speed digital design, so we have to use fine geometry CMOS processes 15:45 We accomplish that with a system of ADCs, not just a single ADC. 16:15 ADC interleaving. If you think about it simply, if you want to double your sample rate you just double the number of ADCs and shift them But this has two problems. First, they still have the same bandwidth. Second, you have to get a very good clock and offset them appropriately 17:00 To get higher bandwidth, you can use a sampler, which is essentially just a very fast switch with higher bandwidth that then delivers the signal to the ADCs at a lower bandwidth But, you have to deal with new problems like intersymbol interference (ISI). 18:20 So, what are the downsides of interleaving? Getting everything to match up is hard, so you have to have a lot of adjustability to calibrate the samplers. For example, if the q levels of one ADC are higher than the other, you'll get a lot of problems. Like frequency spurs and gain spurs. We can minimize this with calibration and some DSP after the fact. 20:00 Triple interleaving vs. double interleaving - the devil is in the details 21:00 Internally, our ADCs are made up of a number of slices of smaller, slower ADCs. 21:15 Internally, we have three teams. An analog ASIC team, a digital ASIC team, and an ADC ASIC team. 22:15 ADC technology is "marching forward at an incredible rate" The off-the-shelf ADC technologies are enabling 5G, 100/400/1T ethernet, and DSP processing. 23:00 Is processing driven by ADCs, or are ADCs advancing processor technology? Both! #engineeringpodcast #podcast #electricalengineerngpodcast #ASIC #ADC #DAC #technology #electronics #electricalengineering